Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers

ABSTRACT

Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

FIELD

[0001] The invention pertains to semiconductor devices and thefabrication thereof, and particularly to ruthenium- andtungsten-containing electrically conductive layers and the formation anduse thereof.

BACKGROUND

[0002] A capacitor generally includes two electrical conductors in closeproximity to, but separated from, each other. The two conductors formthe “plates” of the capacitor, and may be separated by a dielectricmaterial. When a voltage is applied across the plates of a capacitor,electrical charge accumulates on the plates. If the plates areelectrically isolated essentially immediately after a voltage isapplied, the accumulated charge may be stored on the plates, thus“storing” the applied voltage difference.

[0003] The fabrication of integrated circuits involves the formation ofelectrically conductive layers for use as various circuit components,including for use as capacitor plates. Memory circuits, such as DRAMsand the like, use electrically conductive layers to form the opposingplates of storage cell capacitors.

[0004] The drive for higher-performance, lower-cost integrated circuitsdictates ever-decreasing area for individual circuit features, includingstorage capacitors. Since capacitance of a capacitor (the amount ofcharge that can be stored as a function of applied voltage) generallyvaries with the area of capacitor plates, as the circuit area occupiedby the storage capacitor decreases, it is desirable to take steps topreserve or increase capacitance despite the smaller occupied area, sothat circuit function is not compromised.

[0005] Various steps may be taken to increase or preserve capacitancewithout increasing the occupied area. For example, material(s) havinghigher dielectric constant may be used between the capacitor plates.Further, the plate surfaces may be roughened to increase the effectivesurface area of the plates without increasing the area occupied by hecapacitor.

[0006] One method for providing a roughened surface for a plate of astorage cell capacitor is to form the plate of hemispherical grainpolysilicon (HSG), possibly with an overlying metal layer. Thehemispherical grains of HSG enhance the surface area of the platewithout increasing its occupied area.

[0007] HSG presents difficulties in fabrication, however, because of theformation of silicon dioxide on and near the HSG. A silicon dioxidelayer may form on the HSG, particularly during deposition of thecapacitor's dielectric layer. Even with an intervening metal layerpresent, oxygen from the deposition of the dielectric layer can diffusethrough the metal layer, forming silicon dioxide at the polysiliconsurface. Silicon diffusion through the metal layer may also produce asilicon dioxide layer between the metal and the dielectric layers.

[0008] Silicon dioxide between the metal layer and the HSG can degradethe electrical contact to the metal capacitor plate surface. Silicondioxide between the metal layer and the dielectric layer can decreasethe capacitance of the resulting capacitor.

[0009] To attempt to avoid these negative effects caused by formation ofsilicon dioxide, a diffusion barrier layer may be employed between theHSG and the metal layer. However, in the typical capacitor geometry, thegreater the total number of layers, the larger the required minimum areaoccupied by the capacitor. Further, the upper surface of each additionallayer deposited tends to be smoother than the underlying surface,reducing the increased surface area provided by an underlying roughlayer.

[0010] While high-dielectric constant materials are known, many of theseadvantageous materials are formed with processes that are incompatiblewith other materials needed to form capacitors. For example, processesneeded to form a particular dielectric layer can oxidize or otherwiseimpair the properties of the electrode layer on which the dielectriclayer is to be formed. These processes can be incompatible because ofthe necessary process temperatures or process ambients.

[0011] For these reasons, improved materials and methods are needed forforming conducting layers, insulating layers, and capacitors using suchlayers.

SUMMARY

[0012] The present invention provides improved conductive layers,dielectric layers, capacitors, methods for forming such layers, andcapacitors using the layers.

[0013] In a representative embodiment, enhanced-surface-area(rough-surfaced) ruthenium containing electrically conductive layers areprovided. These layers are compatible with high-dielectric-constantmaterials and are useful in the formation of integrated circuits,particularly for plates of storage capacitors in memory cells.

[0014] In one approach, the enhanced-surface-area electricallyconductive layer may be formed by first forming a ruthenium oxidecontaining film or layer. The layer may be stoichiometric ornon-stoichiometric, and may be amorphous or may have both ruthenium (Ru)and ruthenium oxide (RuO₂) phases and may include other materials. Thefilm may be formed, for example, by chemical vapor deposition techniquesor by sputtering or any suitable techniques. The film may be formed overan underlying layer which may be electrically conductive.

[0015] The ruthenium oxide film may be processed at low pressure andhigh temperature—generally at pressures at least about 75 torr or below,desirably about 20 torr or below, most desirably about 5 torr orbelow—and at temperatures in the range of about 500 to 900° C.,desirably about 750 to about 850° C.—so as to convert at least some ofthe ruthenium oxide to ruthenium and to yield a roughenedruthenium-containing layer with a mean grain size desirably in the rangeof about 100 Angstroms or larger.

[0016] The heating process, or anneal, is desirably performed in anon-oxidizing ambient. In an example embodiment, a nitrogen-supplyingambient or nitrogen-supplying reducing ambient may be used during theanneal. A nitrogen-supplying reducing ambient may be used to passivatethe ruthenium for improved compatibility with high-dielectric-constantdielectric materials. In another alternative, a nitrogen-supplyingreducing ambient may be used in a post-anneal to passivate an alreadyroughened layer. In still another alternative, a post-anneal in anoxidizing ambient may be performed, following either the rougheninganneal or the nitride-passivation anneal, as desired. This oxidizingpost-anneal provides oxygen to the roughened layer to reduce thetendency of the ruthenium to scavenge oxygen during later processing.

[0017] The enhanced-surface-area layer may be formed with or without apre-anneal, performed at a higher pressure (such as about 600 torr),before the low pressure, high temperature anneal.

[0018] The roughened layer of ruthenium may be used to provide anenhanced-surface-area electrically conductive layer.

[0019] In an example embodiment, the roughened layer of ruthenium may beformed on an underlying electrically conductive layer, with theroughened layer and the underlying layer together functioning as anenhanced-surface-area electrically conductive layer.

[0020] In another example embodiment, an electrically conductive layermay be formed on or over the roughened layer, with the overlyingelectrically conductive layer and the roughened layer constituting anenhanced-surface area electrically conductive layer.

[0021] In either case, in an example capacitor embodiment for use in anintegrated circuit, the resulting enhanced-surface-area electricallyconductive layer may be used to form a plate of a storage capacitor inan integrated circuit, such as in a memory cell of a DRAM or the like.

[0022] The ruthenium-containing enhanced-surface-area electricallyconductive layer, particularly in the case of an anneal innitrogen-supplying reducing ambient with an oxidizing post-anneal, hasreduced tendency toward oxidation and is thus more compatible with theuse of high-dielectric-constant dielectric materials, while stillproviding enhanced surface area. In addition, even if theruthenium-containing layer oxidizes, it remains conductive. Anadditional metal layer thus may potentially be omitted from thecapacitor structure, allowing smaller dimensions for capacitors with thesame or even greater capacitance.

[0023] In an alternative embodiment, a tungsten nitride layer isprovided as a first electrode layer. A dielectric layer and a secondelectrode layer are conformally applied to the first electrode layer toform a capacitor. The capacitor, or at least the tungsten nitride layer,is annealed at an anneal temperature to increase the capacitance of thecapacitor. In a specific embodiment, the anneal temperature is at least500 C. and the capacitor (or the tungsten nitride layer) is maintainedat the anneal temperature for at least 30 seconds.

[0024] These methods, conductive and dielectric layers, and structuresusing the layers allow the design and fabrication of higher speed,higher density, and lower cost integrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a partial cross-section of layers used in a processaccording to one embodiment, the layers including a ruthenium oxidecontaining layer.

[0026]FIG. 2 is a cross-section of the layers of FIG. 1 after alow-pressure, high-temperature anneal, including a roughened layer.

[0027]FIG. 3 is a partial plan view of the layers of FIG. 2

[0028]FIG. 4 is a cross-section similar to that of FIG. 2 but having anadditional layer underlying the roughened layer.

[0029]FIG. 5 is a cross section of the layers of FIG. 2 after formationof an additional layer overlying the roughened layer.

[0030]FIG. 6 is a cross section of an enhanced-surface-area electricallyconductive layer with a dielectric layer formed thereon according to oneembodiment.

[0031]FIG. 7 is a cross section of the layers of FIG. 6 with anelectrically conductive layer formed on the dielectric layer.

[0032] FIGS. 8A-8B are cross-sections of two embodiments of capacitorstructures that include a roughened layer.

[0033] FIGS. 9A-9C are cross-sections of capacitor structures thatinclude a tungsten nitride electrode layer.

DETAILED DESCRIPTION

[0034] The present invention allows creation of a surface-area-enhancedruthenium electrically conductive layer that has improved compatibilitywith high-dielectric-constant (“high-κ”) dielectric materials ascompared to hemispherical-grain polysilicon (HSG).

[0035] The surface-area-enhanced electrically conductive layer iscreated by heating a film or layer comprising ruthenium oxide such asthe layer 12 of FIG. 1. The heating process, which may anneal the filmor layer, is typically performed at low pressures of less than about 75torr, desirably less than about 20 torr, and most desirably less thanabout 5 torr, and at high temperatures in the range of about 500 to 900°C., desirably about 750 to 850° C. The treatment is desirably performedin a non-oxidizing ambient. The heating process may be performed in anoble ambient, nitrogen ambient, or the like, or in a reducing ambient,which may reduce the temperature required. The heating process may alsobe performed in an electrically neutral environment, or with plasma orglow-discharge assistance or the like, which may also reduce thetemperature required. Heating under relatively low pressure converts atleast a portion of the ruthenium oxide to ruthenium and produces a roughsurface on the layer. Temperature and pressure are preferably selectedso as to enhance the ruthenium oxide to ruthenium conversion.

[0036] The surface-area-enhanced electrically conductive layer may beformed on a supporting structure 10 shown in partial cross-section inFIG. 1. The supporting structure 10 may be any structure present in oron an integrated circuit during the fabrication thereof. In a typicalexample application, the supporting structure may be an electricallyconductive material that will be in electrical contact with a capacitorplate formed by the surface-area-enhanced electrically conductive layer.

[0037] The ruthenium oxide layer 12 may be formed by any suitablemethod. Specific examples of such methods include chemical vapordeposition (CVD) or related process, or sputtering or related process,or the like. The ruthenium oxide layer may be stoichiometric rutheniumoxide (RuO₂) or non-stoichiometric ruthenium oxide (RuO_(x)).

[0038] If the layer 12 is formed via CVD, the deposition may beperformed, for example, at pressures of 1-20 torr, desirably about 5torr. The oxygen may be supplied in the form of O₂ or other oxidizinggas, such as N₂O, NO, or ozone (O₃). The oxygenating gas and a rutheniumprecursor, and suitable diluent gasses, if desired, may be supplied atsuitable flow rates, such as in the range of about 100-2000 sccm.Alternatively, the ruthenium precursor can be deliver by directvaporization. Deposition may be performed for a time in the range ofabout 10 to 500 seconds, desirably for sufficient time and undersufficient conditions to deposit RuO_(x) or RuO₂ to a thickness in therange of about 100 to 600 Angstroms.

[0039] The resulting ruthenium oxide layer 12 may optionally bepre-annealed, such as by rapid thermal anneal (RTA) in hydrogen or othersuitable anneal environment at pressures in the range of 500 to 700 torrand temperatures in the range of 500 to 900° C. The pre-annealstabilizes the film, promoting crystallization of ruthenium andruthenium oxide phases.

[0040] The ruthenium oxide layer 12, with or without a pre-anneal, isthen treated at low pressure and high temperature as described above.The treatment may reduce the proportion of ruthenium oxide in the layerand increase the proportion of ruthenium. The ruthenium oxide in theruthenium oxide layer 12 is partially or completely converted toruthenium by the anneal, leaving an enhanced-surface-area layer 16 shownin the cross section of FIG. 2. While the enhanced-surface-area layer 16is referred to by separate reference character for convenience herein,it should be noted that the layer 16 is formed from the layer 12, and isthe same layer in that sense. FIG. 3 shows a partial plan view of theroughened ruthenium layer 16 of FIG. 2. Although the example roughenedruthenium layer 16 shown in the figures is discontinuous, this is by wayof example only and continuous films may also be produced. Increasedthickness of the initial layer 12 tends to produce more continuousfilms, as does reduced temperature and increased pressure during theanneal and reduced anneal time.

[0041] The anneal may be performed in a noble, nitrogen, or reducingambient or the like. As an additional example embodiment, an anneal maybe performed in a nitrogen-supplying reducing ambient such as such asammonia, nitrogen, a nitrogen and hydrogen mixture, and the like. Theanneal parameters may be selected such that “nitrogen-passivated”ruthenium in the form of RuN_(x) is formed in the layer 16, at leastnear the outermost surfaces thereof, passivating the layer 16.

[0042] As another example alternative, nitride passivation may be usedin the form of a post-anneal in a nitrogen-supplying reducing ambient.

[0043] As yet another variation, a desirably brief post-anneal in anoxidizing ambient such as oxygen or ozone may be performed on thealready roughened layer 16, to form “oxygen-passivated” ruthenium orruthenium nitride in the outermost portions of the layer 16(RuO_(x)N_(y) or RuO_(x)), in order to reduce or prevent the rutheniumfrom later scavenging oxygen from a nearby dielectric material. Theoxidizing post-anneal may optionally follow a nitride passivationpost-anneal.

[0044] As indicated in FIG. 2, the roughened ruthenium layer 16,together with the supporting structure 10 if electrically conductive,may together constitute an enhanced-surface-area electrically conductivelayer 26 compatible with high-dielectric-constant dielectric materials.

[0045] The layer 16 produced such as described above may also be used incooperation with other layers. This may be useful in cases where thesupporting structure 10 may not be electrically conductive or may beincompatible with high-dielectric-constant dielectric materials. In thediscussion and claims herein, “on” used with respect to two layers, one“on” the other, means at least some contact between the layers, while“over” means the layers are in close proximity, but possibly with one ormore additional intervening layers such that contact is not required.Neither “on” nor “over” implies any directionality as used herein.

[0046] As shown, for example, in FIG. 4, a layer 22 of material may beformed over the supporting structure 10, with the roughened rutheniumlayer 16 then formed on the layer 22. The layer 22 may be anelectrically conductive layer to electrically connect all portions oflayer 16. The layer 22 may also act as a barrier layer to preventcontact between high-dielectric-constant dielectrics, to be used forcapacitor formation, and the supporting structure 10. If the layer 22 isan electrically conductive layer, layer 22 together with layer 16constitute an enhanced-surface-area electrically conductive layer 26.Any compatible electrically conductive material may be used, such as Pt,Ir, IrO_(x), Rh, RuSi_(x), and SrRuO_(x) and alloys thereof as well asRuSiO_(x) and RuSiN_(x), for example.

[0047] Alternatively, as shown for example in FIG. 5, a layer 24 ofelectrically conductive material may be formed conformally over thelayer 16 and over the supporting structure 10. The layer 24, togetherwith the layer 16, then constitutes an enhanced-surface-areaelectrically conductive layer 26. As with the layer 22, the layer 24 mayfunction to electrically connect all portions of layer 16, and may alsofunction as a barrier layer to prevent contact betweenhigh-dielectric-constant dielectrics and the supporting structure 10.Examples of such electrically conductive materials include the materialslisted in the preceding paragraph. Ruthenium oxide is a desirablematerial because of compatibility with the underlying ruthenium layer16.

[0048] As described by way of example above with reference to FIGS. 3-6,the supporting structure 10 and/or one or more layers above or below thelayer 16 (or both) may be electrically conductive and may be employed asneeded to obtain conductivity and other desired properties. Theresulting enhanced-surface-area electrically conductive layer 26, shownby way of example in FIGS. 3, 5, and 6, is represented generically aslayer 26 in FIG. 6. To form a capacitor with the enhanced-surface-areaelectrically conductive layer 26, a layer 28 of dielectric material,most desirably a high-dielectric-constant dielectric material (generallyany dielectric with a dielectric constant of at least 9), such astantalum pentoxide (Ta₂O₅), may be formed conformally over theenhanced-surface-area electrically conductive layer, as shown in FIG. 6.Other high-constant dielectrics may also be employed, such as bariumstrontium titanium oxide (Ba,Sr)TiO₃, lead zirconium titanium oxidePb(Zr,Ti)O₃, and strontium bismuth tantalum oxide (SrBi₂Ta₂O₉), forexample. The layer 28 is desirably sufficiently thin and conforming toprovide an at least somewhat enhanced surface area on the surface awayfrom the layer 26.

[0049] An electrically conductive layer 30 may then be formedconformally over the dielectric layer 28, as shown in FIG. 7. Thesurface of layer 30 uppermost in the figure is not shown because thelayer may generally be of any thickness sufficiently thick to insurecontinuity of the layer and sufficiently thin to fit within the overallvolume allotted to the capacitor. As shown in FIG. 7, the surface oflayer 30 next to the dielectric layer 28 desirably conforms to theenhanced surface area of the dielectric layer 28, providing an enhancedsurface area for the electrically conductive layer 30 as well. The twoelectrically conductive layers, layers 26 and 30, form the two plates ofa capacitor. Both plates desirably have enhanced surface area relativeto the area occupied by the capacitor.

[0050] Application of the plate structure shown in FIG. 7 to a containercapacitor is illustrated in the cross-section of a container capacitorshown in FIG. 8A. The supporting structure 10 may be an electricallyconductive plug of polysilicon or other electrically conductive materialformed at the bottom of an opening in a dielectric material 32 such asborophosphosilicate glass (BPSG). The lower end of the plug typicallyelectrically contacts a circuit element such as a transistor gate (notshown). At the sides of the cylindrical container, the BPSG itselffunctions a supporting structure for the capacitor plate structure. Therelative thinness of the capacitor structure provided by the layerstructure of FIG. 7 maximizes the capacitor plate surface area in thecontainer capacitor of FIG. 8A, particularly for the inner (upper)electrode, the surface area of which decreases most rapidly withincreasing thickness of the layer structure. The use of theenhanced-surface-area ruthenium electrically conductive layer thusprovides improved capacitance in a given area.

[0051] Application of the plate structure shown in FIG. 7 to a studcapacitor is illustrated in the cross-section of a stud capacitor shownin FIG. 8B. The supporting structure 10 includes a plug 25 that extendsfrom a surface 27 and the layers 26, 28, 30 are formed conformally onthe plug 25.

[0052] In a specific example, ruthenium oxide was deposited onsubstrates of BPSG to a thickness of about 600 Angstroms by CVD. Theruthenium oxide layers were pre-annealed in nitrogen for one minute at800° C. and 600 torr, then annealed at 800° C. in nitrogen for varyingtimes and at varying pressures. Such a pre-anneal can be omitted.

[0053] On SEM examination, layers annealed for eight minutes at 4.5 torrshowed marked surface roughness with mean grain size of about 100Angstroms or larger, with good uniformity over the substrate surface.Layers annealed for eight minutes at 60 torr showed some surfaceroughness with a mean grain approaching 100 Angstroms, but withgenerally less roughness than at 4.5 torr. Layers annealed for eightminutes at 600 torr showed generally still less roughness and stillsmaller grain sizes than at 60 torr. Layers annealed for two minutes at4.5 torr also showed a marked surface roughness, with possibly slightlyless uniformity over the substrate surface than those annealed for eightminutes. X-ray diffraction studies of the annealed layers showedruthenium as the primary constituent but the Ru/RuO₂ ratio varied withprocessing conditions.

[0054] Superior capacitors including metal-insulator-metal (MIM)capacitors can be obtained using a tungsten nitride layer as anelectrode. The tungsten nitride layer can be formed by reactivesputtering of a tungsten target in a nitrogen containing ambient, or bya chemical vapor deposition process (CVD) such as a plasma enhanced CVD(PECVD), a metallo-organic CVD (MOCVD) process, atomic layer deposition(ALD), or other process. The tungsten nitride layer is convenientlyformed using a thermal CVD process using tungsten fluoride (WF₆) andammonia (NH₃) as precursors, and a 300 Angstrom thick layer can beformed using such a process in about 1-3 minutes. The thickness of thetungsten nitride layer can be varied but typically the thickness is inthe range of 100-1000 Angstroms.

[0055] As deposited, the tungsten nitride layer can contain a mixture ofa stable tungsten nitride compound W₂N and a metastable tungsten nitridecompound WN. The metastable compound WN can be converted to the stabletungsten nitride compound W₂N in a rapid thermal process (RTP) in whichthe temperature of the tungsten nitride layer is rapidly raised to ananneal temperature in the range of 600-800 C. and held at the annealtemperature for about 60 seconds. Typically, the temperature of thetungsten nitride layer is ramped up to and down from an annealtemperature of 700 C. in less than about 30 seconds. Such an annealprocess is typically performed before a dielectric layer and a secondelectrode are formed on the tungsten nitride layer so that a capacitorstructure is otherwise complete. The metastable compound WN may includedefects and may be preferentially oxidized during deposition ofdielectric materials such as Ta₂O₅ and subsequent annealing processes.Therefore, the capacitance of a capacitor formed without an annealprocess tends to be low. In addition, the presence of defects tends toincrease leakage currents. In a completed capacitor, the anneal processtends to increase capacitance by about 20% with respect to a capacitorwithout annealing and to reduce leakage currents that occur whenvoltages are applied to the electrodes.

[0056] A dielectric layer consisting of any of various dielectricmaterials is formed on the tungsten nitride layer. Suitable dielectricmaterials include high-dielectric-constant materials such as tantalumpentoxide (Ta₂O₅), doped Ta₂O₅ such as Ti-doped Ta₂O₅, barium strontiumtitanium oxide (Ba,Sr)TiO₃, lead zirconium titanium oxide Pb(Zr,Ti)O₃,strontium bismuth tantalum oxide (SrBi₂Ta₂O₉), BaTiO₃, SrTiO₃,Pb(Zr,Ti)O₃, SrBi₂Ta₂O₉, SrBi₂Nb₂O₉, SrBi₂(Nb,Ta)₂O₉, (Pb,La)(Zr,Ti)O₃,Al₂O₃, ZrO₂, HfO₂, and SiO_(x)N_(y). For Ta₂O₅, formation of astoichiometric compound is preferred so that the Ta₂O₅ layer is not atantalum rich layer, because tantalum rich Ta₂O₅ layers tend to beconducting, not insulating. Tantalum pentoxide dielectric layers arepreferred in some applications because of its large dielectric constantand its stability. However, tantalum pentoxide is typically formed usinga MOCVD process in an oxidizing ambient such as an oxygen, ozone, or N₂Oambient. While many electrode layer materials cannot be exposed tooxidizing ambients, tungsten nitride is relatively unaffected by suchambients and therefore facilitates the use of tantalum pentoxidedielectric layers.

[0057] An electrode layer of tungsten nitride or other conductingmaterial is formed on the dielectric layer and serves as a top electrodefor the capacitor. Other suitable conducting materials include TiN,TiON, WN_(x), TaN, Ta, Pt, Rh, Pt-Rh, Pt-RhO_(x), Ru, RuO_(x), Ir,IrO_(x), Pt-Ru, Pt-RuO_(x), Pt-Ir, Pt-IrO_(x), SrRuO₃, Au, Pd, Al, Mo,Ag, polysilicon, and alloys thereof. These electrode materials can beformed by various processes. For example, ruthenium and platinum/rhodiumare conveniently formed using a CVD process. After the dielectric layerand the electrode layers are formed, the capacitor is annealed asdescribed above.

[0058] FIGS. 9A-9C illustrate several example capacitor geometries thatinclude tungsten nitride electrodes. Referring to FIG. 9A, a platecapacitor 51 is formed on a surface of a substrate 53. The substrate 53can be any of various substrate materials including GaAs, silicon, orBPSG. The capacitor 51 includes a first electrode 55, a second electrode57, and a dielectric layer 59. In a representative example, the firstelectrode 55 is a tungsten nitride layer, the dielectric layer 58 is aTa₂O₅ layer, the second electrode is a TiN layer, and the substrate 53is BPSG.

[0059] When voltages are applied to electrodes of a capacitor such asthe capacitor 51, some electrical current flows between the electrodes.This current is generally undesirable and is referred to as a “leakage”current. Plate capacitors having electrodes of tungsten nitride haveleakage currents of as little as about 20 nA/cm², or as low as about 5nA/cm² for capacitors having dielectric layers 100 Angstroms thick andwith an applied voltage of 1 V.

[0060] With reference to FIG. 9B, a container capacitor 61 is formed inan etched recess 62 in a substrate 63. A tungsten nitride electrodelayer 65 covers a bottom surface 66 and a side surface 67 of the recess62. A Ta₂O₅ dielectric layer 69 covers the electrode layer 65,substantially filling the recess 62 and a tungsten nitride electrodelayer 71 (or other conductive layer) covers the dielectric layer 69. Thedimensions of the recess 62 are selected to provide a desiredcapacitance, and can be selected in conjunction with a minimum featuresize for other circuit elements that are formed on the substrate 63. Ina representative example, the recess 62 has a diameter D of 200 nm and adepth Z of 1000 nm. For these dimensions, the tungsten nitride layer ispreferably about 300 Angstroms (30 nm) thick. Tungsten nitride layersthinner than about 100 Angstroms (10 nm) tend to have voids. Because ofthese voids, such layers do not act as continuous electrodes, reducingthe capacitance of the capacitor 61. Tungsten nitride layers thickerthan about 1000 Angstroms (100 nm) tend to occupy too much of the volumeof the recess 62, also limiting the capacitance of the capacitor 61. Forcontainer capacitors formed in larger recesses, thicker tungsten nitridelayers can be used without sacrificing too much capacitance.

[0061] The recess 62 is generally formed in the substrate 63 with anetching process. If the substrate 63 is BPSG, the recess 62 can beformed with a dry etch process such as plasma etching. While otheretching processes are possible, because the recess 62 is deeper thanwide, a selected etch process is preferably anisotropic.

[0062] Referring to FIG. 9C, a stud capacitor 71 is formed on a plug 73that extends from a surface 75 of a substrate 77. A tungsten nitrideelectrode layer 79 is formed on the plug 73 and is covered with adielectric layer 81 and an electrode layer 83. The dielectric layer 81and the electrode layer can be formed of any of the materials mentionedabove. Representative materials are Ta₂O₅ and TiN for the dielectriclayer 81 and the electrode layer 83, respectively. The plug 73 may be anelectrically conductive plug of polysilicon or other electricallyconductive material formed in a recess in the substrate 77 such as aborophosphosilicate glass (BPSG). The lower end of the plug typicallyelectrically contacts a circuit element such as a transistor gate (notshown).

[0063] In the above examples, a tungsten nitride layer is depositeddirectly on a substrate such as BPSG. Alternatively, a tungsten nitridelayer can be formed or deposited on a titanium nitride (TiN) adhesionlayer, or other adhesion layer, to improve the bonding of the tungstennitride layer to the substrate.

[0064] Variations within the scope and spirit of the disclosure abovewill be apparent to those of ordinary skill in the art. For example, theenhanced-surface-area layers can be used in ferroelectric memories toimprove storage capacity. The scope of coverage is accordingly definednot by the particular example embodiments and variations explicitlydescribed above, but by the claims below.

We claim:
 1. A method of forming an enhanced-surface-area electricallyconductive structure, the method comprising: providing a layercontaining ruthenium oxide; converting at least a portion of theruthenium oxide in the layer to ruthenium so as to produce aruthenium-containing layer having a rough surface.
 2. The method ofclaim 1 wherein the act of converting comprises heating the layer. 3.The method of claim 1 wherein the act of converting comprises exposingthe layer to a reducing ambient.
 4. The method of claim 1 wherein theact of converting comprises exposing the layer to a reduced-pressureenvironment.
 5. The method of claim 1 wherein the step of convertingcomprises converting at least a portion of the ruthenium oxide in thelayer to ruthenium so as to produce a layer having a textured surfacewith a mean feature size of at least about 100 Angstroms.
 6. A method offorming an enhanced-surface-area electrically conductive structure, themethod comprising: providing a layer containing ruthenium oxide;converting at least a portion of the ruthenium oxide to ruthenium byheating the layer in a reduced-pressure environment with a pressure ofabout 75 torr or less so as to produce a layer having a rough surface.7. The method of claim 6 wherein the step of converting is performed ina reduced-pressure environment with a pressure of about 20 torr or less.8. The method of claim 6 wherein the step of converting is performed ina reduced-pressure environment with a pressure of about 5 torr or less.9. A method of forming an enhanced-surface-area electrically conductivestructure, the method comprising: providing a layer containing rutheniumoxide; converting at least a portion of the ruthenium oxide to rutheniumby heating the layer to at least about 500° C. in a reduced-pressureenvironment with a pressure of about 75 torr or less for a sufficienttime so as to produce a layer having a rough surface.
 10. The method ofclaim 9 wherein the act of converting is performed by heating the layerto at least about 750° C.
 11. The method of claim 9 wherein the act ofconverting is performed by heating the layer to at least about 800° C.12. The method of claim 9 wherein the act of converting is performed byheating the layer to at least about 500° C. for at least about 2minutes.
 13. The method of claim 9 wherein the act of converting isperformed by heating the layer to at least about 500° C. for a time inthe range of about 2 to about 20 minutes.
 14. A method of forming anenhanced-surface-area electrically conductive structure, the methodcomprising: providing a layer containing ruthenium oxide; and convertingthe ruthenium oxide in the layer to ruthenium so as to produce aruthenium-containing layer having a rough surface.
 15. A method offorming an enhanced-surface-area electrically conductive structure, themethod comprising: providing a layer containing ruthenium oxide;converting some ruthenium oxide in the layer to ruthenium so as toproduce a ruthenium-containing layer having a rough surface; andexposing the layer having a rough surface to a ambient suitable todecrease the tendency of the layer to react with surrounding material.16. The method of claim 15 wherein the act of exposing comprisesexposing the layer having a rough surface to an oxidizing ambient. 17.The method of claim 15 wherein the act of exposing comprises exposingthe layer having a rough surface to nitrogen ambient.
 18. The method ofclaim 15 wherein the act of exposing comprises exposing the layer havinga rough surface to a nitrogen-supplying reducing ambient.
 19. The methodof claim 15 wherein the act of exposing comprises exposing the layerhaving a rough surface first to a nitrogen-supplying reducing ambientthen to an oxidizing ambient.
 20. A method of forming anenhanced-surface-area electrically conductive structure, the methodcomprising: providing a layer containing ruthenium oxide; and convertingsome ruthenium oxide in the layer to ruthenium by heating the layer in areduced-pressure environment in a non-oxidizing ambient so as to producea ruthenium-containing layer having a rough surface.
 21. The method ofclaim 20 wherein the act of converting is performed in a nitrogenambient.
 22. The method of claim 20 wherein the act of converting isperformed in a reducing ambient.
 23. The method of claim 20 wherein theact of converting is performed in a nitrogen-supplying reducing ambient.24. The method of claim 20 wherein the act of converting is performed inan ammonia-containing ambient.
 25. The method of claim 20, wherein theact of converting is performed in a hydrogen-containing ambient.
 26. Themethod of claim 20, wherein the art of converting is performed in ahelium-containing ambient.
 27. The method of claim 20, wherein the artof converting is performed in a neon-containing ambient.
 28. The methodof claim 20, wherein the art of converting is performed in anargon-containing ambient.
 29. The method of claim 20 further comprisingexposing the layer having a rough surface to an oxidizing ambient.
 30. Amethod of forming an enhanced-surface-area electrically conductivelayer, the method comprising: providing a layer containing rutheniumoxide; selecting anneal conditions adapted to convert at least a portionof the ruthenium oxide to ruthenium; and annealing the layer under saidconditions so as to produce a layer having a rough surface.
 31. A methodof forming a ruthenium-containing enhanced-surface-area electricallyconductive layer, the method comprising: depositing a layer consistingessentially of ruthenium oxide onto a supporting structure; andannealing the layer in reduced pressure environment in a non-oxidizingambient so as to substantially convert the ruthenium oxide to ruthenium,leaving a roughened layer consisting essentially of ruthenium on thesupporting structure.
 32. A method of forming an enhanced-surface-areaelectrically conductive layer, the method comprising: forming a layer ofconducting material; forming a layer comprising ruthenium oxide on thelayer of conducting material; and annealing the layer comprisingruthenium oxide so as to convert at least some of the ruthenium oxide toruthenium so as to produce a layer having a textured surface with a meanfeature size of about 100 Angstroms or more.
 33. A method of forming anenhanced-surface-area electrically conductive layer, the methodcomprising: providing a layer comprising ruthenium oxide; annealing thelayer comprising ruthenium oxide so as to convert at least some of theruthenium oxide to ruthenium so as to produce a resulting layer having atextured surface with a mean feature size of about 100 Angstroms ormore; and forming a layer of electrically conductive materialconformally over the resulting layer such that the surface of theconductive material away from the resulting layer has a textured surfacegenerally corresponding to that of the resulting layer.
 34. A method offorming a capacitor, the method comprising: providing a layer containingruthenium oxide; converting least some of the ruthenium oxide toruthenium so as to produce a resulting layer having a rough surface;forming a layer of dielectric material over the resulting layer; andforming a layer of conductive material over the layer of dielectricmaterial.
 35. The method of claim 34 wherein the act of forming a layerof dielectric material comprises forming a layer ofhigh-dielectric-constant dielectric material.
 36. The method of claim34, wherein at least some of the ruthenium oxide is converted toruthenium by annealing the layer at a pressure of 75 torr or less. 37.The method of claim 34, further comprising processing the layercontaining ruthenium oxide to define a first electrode.
 38. The methodof claim 37, wherein the first electrode is defined by an etchingprocess.
 39. The method of claim 37, wherein the first electrode isdefined by a chemical-mechanical polishing process.
 40. The method ofclaim 37, wherein the first electrode is defined prior to converting atleast some of the ruthenium oxide to ruthenium.
 41. A method of forminga capacitor, the method comprising: providing a first layer ofelectrically conductive material; forming a layer containing rutheniumoxide on the layer of electrically conductive material; annealing thelayer containing ruthenium oxide so as to convert at least some of theruthenium oxide to ruthenium and so as to produce a rough resultingsurface with a mean grain size of at least about 100 Angstroms; forminga layer of dielectric material over the layer having a rough surface;and forming a second layer of conductive material over the layer ofdielectric material.
 42. The method of claim 41 wherein the act offorming a layer of dielectric material comprises forming a layer ofhigh-dielectric-constant dielectric material.
 43. A method of forming acapacitor, the method comprising: forming a first conductive layercontaining tungsten nitride; forming a layer of dielectric material overthe first conductive layer; and forming a second conductive layer overthe layer of dielectric material.
 44. The method of claim 43, furthercomprising annealing at least the first conductive layer at an annealtemperature sufficient to convert a tungsten nitride compound WN into atungsten nitride compound W₂N.
 45. The method of claim 44, wherein theanneal temperature is at least 500 C. and the first conductive layer ismaintained at the anneal temperature for at least 30 seconds.
 46. Themethod of claim 44, wherein the first conductive layer is formedconformally on a post.
 47. The method of claim 44, wherein the firstconductive layer is formed conformally in a recess in a substrate. 48.The method of claim 44, where the dielectric layer contains tantalumoxide.
 49. A method of increasing a capacitance of a capacitor thatincludes a tungsten nitride electrode, the method comprising annealingthe tungsten nitride layer at an anneal temperature sufficient toconvert WN into W₂N.
 50. The method of claim 49, wherein the annealtemperature is at least 500 C.
 51. An integrated circuit comprising anenhanced-surface-area electrically conductive ruthenium-containing layerhaving a textured surface with a mean feature size of at least about 100Angstroms.
 52. An integrated circuit comprising an enhanced-surface-areaelectrically conductive nitrogen-passivated ruthenium-containing layerhaving a textured surface with a mean feature size of at least about 100Angstroms.
 53. An integrated circuit comprising an enhanced-surface-areaelectrically conductive nitrogen-passivated and oxygen-passivatedruthenium-containing layer having a textured surface with a mean featuresize of at least about 100 Angstroms.
 54. An integrated circuitcomprising a nitrogen-passivated ruthenium-containing layer.
 55. Anintegrated circuit comprising a nitrogen-passivated andoxygen-passivated ruthenium-containing layer.
 56. An integrated circuitcomprising an annealed tungsten nitride electrode layer.
 57. Theintegrated circuit of claim 56, wherein the annealed tungsten nitrideelectrode layer consists essentially of W₂N.
 58. The integrated circuitof claim 56, further comprising a dielectric layer of tantalum pentoxidethat covers the annealed tungsten nitride layer.
 59. A method of forminga passivated layer of ruthenium or ruthenium oxide during fabrication ofan electronic device, the method comprising: providing a layer ofruthenium or ruthenium oxide; and annealing the layer in anitrogen-supplying or nitrogen-supplying and reducing ambient so as topassivate the layer.
 60. The method of claim 59 further comprisingannealing the layer in an oxidizing ambient.
 61. The method of claim 59wherein the act of annealing comprises annealing in an ammonia ambient.62. The method of claim 59 wherein the act of annealing comprisesannealing in a mixture comprising hydrogen and nitrogen.
 63. The methodof claim 59 wherein the act of annealing comprises annealing innitrogen.
 64. A method of applying a conductive film, the methodcomprising: applying a layer of tungsten nitride; and annealing thetungsten nitride layer.
 65. The method of claim 64, wherein the tungstennitride layer includes a metastable tungsten nitride compound and thetungsten nitride layer is annealed at a temperature sufficient toconvert at least some of the metastable compound to a stable compound.66. A method of forming an array of capacitors, the method comprising:providing a layer containing ruthenium oxide; converting at least someof the ruthenium oxide to ruthenium so as to produce a resulting layerhaving a rough surface; forming a layer of dielectric material over theresulting layer; forming a conductive layer on the layer of dielectricmaterial; and defining an array of electrodes by patterning at least oneof the ruthenium oxide layer or the resulting layer.
 67. The method ofclaim 66, wherein the array of electrodes is defined prior to formingthe layer of dielectric material.
 68. The method of claim 66, whereinthe array of electrodes is defined after forming the conductive layer onthe dielectric layer.
 69. The method of claim 65, wherein the array ofelectrodes is defined by etching.
 70. The method of claim 65, whereinthe array of electrodes is defined by chemical-mechanical polishing. 71.A DRAM, comprising an array of capacitors that includes electrodesdefined in an enhanced-surface-area electrically conductive layer havinga textured surface area with a mean surface area of about 100 Angstroms.